6845 CRT Controller
The 6845 Cathode Ray Tube
(CRT) Controller interfaces a microprocessor to a raster-scan CRT
display. The microprocessor can access 19 registers that in turn work
with the CRT Controller control logic to generate display timing signals
(Horizontal Sync, Vertical Sync, and Display Enable); memory addresses
(14-bit Refresh Memory Address and 5-bit Row Address) for alphanumeric
display memory subsystems; a cursor output (a single signal, Cursor)
which is valid for the current Refresh Memory Address and Row Address
outputs; and, light pen strobe input (a single signal, LPSTB) which
forces the internal capture of the Refresh Memory Address for read by
The primary function of the
CRTC is to generate refresh addresses (MA0-MA13), row selects (RA0-RA4),
and video monitor timing (HSYNC, VSYNC) and Display Enable. Other
functions include an internal cursor register which generates a Cursor
output when its contents compare to the current Refresh Address. A
light-pen strobe input signal allows capture of Refresh Address in an
internal light pen register.
All timing in the CRTC is derived from the CLK input. In alphanumeric
terminals, this signal is the character rate. Character rate is divided
down from video rate by external High Speed Timing when the video
frequency is greater than 3MHz. Shift Register, Latch, and MUX Control
signals are also provided by the external High Speed Timing.
The processor communicates with the CRTC through a buffered 8-bit Data
Bus by reading/writing into the 18-register file of the CRTC.
The Refresh Memory address is multiplexed between the Processor and the
CRTC. Data appears on a Secondary Bus which is buffered from the
processor Primary Bus. A number of approaches are possible for solving
contentions for the Refresh Memory.
Processor always get
Processor gets priority
access anytime, but can be synchronized by an interrupt to perform
accesses only during horizontal and vertical retrace times.
Synchronize processor by
memory wait cycles.
Synchronize processor to
character rate. The 6800 MPU family lends itself to this configuration
because it has constant cycle lengths. This method provides zero burden
on the processor because there is never a contention for memory. All
accesses are "transparent".
The secondary data bus
concept is in no way precludes using the Refresh RAM for other purposes.
It looks like any other RAM to the Processor. For example, using
Approach 4, a 64K byte RAM Refresh Memory could perfrom refresh and
progamme storage functions transparently.
The CRTC consists of programmable horizontal and vertical timing
generators, programmable linear address register, programmable cursor
logic, light pen capture register, and control circuitry for interface
to a processor bus.
All CRTC timing is derived from CLK, usually the output of an external
dot rate counter. Coincidence (CO) circuits continuously compare counter
contents to the contents of the programmable register file, R0-R17. For
horizontal timing generation, comparisons result in: (1) Horizontal sync
pulse (HS) of a frequency, position, and duration determined by the
The Horizontal counter produces H clock wich drives the Scan Line
Counter and, Vertical Control. The contents of the Raster Counter are
continuously compared to the Max Scan Line Address Register. A
coincidence resets the Raster Counter and clocks the Vertical Counter.
Comparisons of Vertical Counter contents and Vertical Registers result
in: (1) Vertical sync pulse (VS) of a frequency and position determined
by the register - the width is fixed at 16 raster lines in the vertical
control section and is not programmable, (2) Vertical Display of a
frequency and position determined by the registers.
The Vertical Control Logic has other functions:
Generate row selects,
RA0-RA4, from the Raster Count for the corresponding interlace or
Extend the number of scan
lines in the vertical total by the amount programmed in the Vertical
Total Adjust Register.
The Linear Address Generator
is driven by CLK and locates the relative positions of characters in
memory with their positions on the screen. Fourteen lines, MA0-MA13, are
available for addressing up to four pages of 4K characters, 8 pages of
2K characters, etc. Using the Start Address Register, hardware scrolling
through 16K characters is possible. The Linear Address Generator repeats
the same sequence of addresses for each scan line of a character row.
Source: Tomas Karlsson